The present invention relates to a method and to a device for the permanent storage of data, wherein, in particular, the advantages of a bitline inversion coding are to be exploited.
Permanent storage devices, so-called ROM (read-only memory) storage devices used in current electronic systems are based on the fact that, in the memory production process, one of two possible states is respectively assigned to memory cells of the memory, in order thereby to store a first and a second value respectively. In this case, for example, a first state of the memory cell encodes a binary value “0”, whilst a second state encodes a binary value “1”. The memory cells are addressable via wordlines and bitlines, such that the state of the individual memory cells can be evaluated via the corresponding bitline.
FIG. 5 shows, exemplarily, a portion of a memory cell arrangement such as that used in a typical ROM memory according to the prior art. The memory cells 100 are arranged in the form of an array, and are addressable through wordlines WL and bitlines BL0, BL1, BL2, BL3. Each of the memory cells 100 comprises a switching means 110 in the form of an NMOS transistor. Alternatively, PMOS transistors or other forms of switching means may be used. One input of the switching means 110 is in each case connected to a fixed potential, in this case a negative supply voltage of the memory. The other input of the switching means 110 is selectively connected to one of the bitlines BL0, BL1, BL2, BL3, depending on which state has been assigned to the memory cell 100. More precisely, this means that, for a first state of the memory cell 100, a connection to the bitline BL0, BL1, BL2, BL3 is provided at a connection point provided for that purpose, whilst, for a second state of the memory cell 100, the connection to the bitline BL0, BL1, BL2, BL3 is not provided. In essence, read-out of the memory is effected in that the bitlines BL0, BL1, BL2, BL3 are connected for a certain period to a further fixed potential, in this case to a positive supply voltage of the memory, in order to effect a precharging of the bitlines BL0, BL1, BL2, BL3. For the actual read-out process, a signal is then applied to one of the wordlines WL that is connected to the control inputs of the switching means 110, in such a way that the switching means 110 activated through this wordline WL connect their two inputs in a conductive manner. A connection of the bitline BL0, BL1, BL2, BL3 to the negative supply voltage is thus established for each of the memory cells 100 that is activated through the wordline WL and to which the first state has been assigned, such that the bitline BL0, BL1, BL2, BL3 is discharged. Consequently, the state of the memory cells 100 can be evaluated through measurement of the charge state of the bitline BL0, BL1, BL2, BL3.
In the case of large storage devices, it is usual to organise the memory cells in rows and columns. In this case, a plurality of bitlines, for example 8, 16, 32 or 64, are combined to form one column and use a common output structure via which the evaluation of the bitlines is effected, the invention being described exemplarily in the following, for simplicity, with reference to 8 bitlines. In order to render this possible, column multiplexers are used, which respectively further connect one of the bitlines supplied to them to the output structure, in dependence on a control signal.
A problem of the ROM storage devices according to the prior art described above, however, is that an unfavourable distribution of the states of memory cells that are assigned to a bitline can result in a high additional load for this bitline. This problem may be explained as follows, with reference to FIG. 5: For the memory cells 100, to which the first state has been assigned, a connection to the negative supply voltage is provided via the switching means 110. These connections result in, for example, an additional capacitive load and additional leakage currents. The more the first state has been assigned to the memory cells 100 belonging to the bitline, the higher is this load.
In view of the problem stated above, there is known from U.S. Pat. No. 6,424,556 B1 the practice of performing a so-called bitline inversion coding, in which the assignment of the first state and of the second state of the memory cells to the first and second binary value is inverted, in order to achieve a lesser capacitive load for a bitline or for certain memory areas. This would mean, for example, that a bitline, for which provision is made whereby the majority of the memory cells store the binary value “0”, is used with an inverted assignment, as a bitline the majority of whose memory cells store the binary value “1”. In this way, it is possible to achieve a situation for both cases, i.e. a majority storage of a “0” or a majority storage of a “1”, in which the majority of the memory cells of the respective bitline assumes the state which means the least additional load for the bitline.
In the read-out of the memory cells, it is consequently necessary to take into account whether the instantaneously evaluated bitline is based on an inverted or non-inverted assignment of the state of the memory cells to the binary values “0” and “1”. This is typically effected in that there are additionally stored in the storage bitline inversion coding data which define whether the bitlines are respectively based on the non-inverted assignment or the inverted assignment.
An example of a circuit arrangement for the read-out of a storage with a bitline inversion coding according to the prior art is represented in FIG. 6. Bitlines BL0-BL7 of an arrangement of memory cells (not shown) are supplied to a column multiplexer 210. The column multiplexer 210, in dependence on a control signal having sub-signals Y0-Y7, forwards the signal of respectively one of the bitlines BL0-BL7 to a data line DL. For this purpose, the column multiplexer 210 comprises switching means 214 in the form of NMOS transistors. The switching means 214 are respectively connected, at an input, to a corresponding bitline BL0-BL7 and, at their other input, to the data line DL. The switching means 214 are activated via a respective inverter 212 of one of the sub-signals Y0-Y7 of the control signal of the column multiplexer 210.
At a further input, a reference bitline BLref is supplied to the column multiplexer 210. A switching means 214, which likewise consists of an NMOS transistor, forwards the signal of the reference bitline BLref to a reference data line DLREF. Like the switching means 214 of the bitlines BL0-BL7, the switching means 214 of the reference bitline BLref is activated, via an inverter 212, through a reference bitline control signal Yref.
The data line DL and the reference data line DLREF are supplied to an inverting measuring amplifier 230, which is of differential design and measures the charge state of the bitline BL0-BL7 connected to the data line DL relative to the charge state of the reference bitline BLref.
The output signal of the measuring amplifier 230 is supplied to an inverting means 240. The inverting means 240 comprises two signal paths, of which a first signal path comprises two series-connected inverters 242, 244 and a second signal path comprises one inverter 246. One of the inverters 242, 244 of the first signal path is activated through a control signal ENB, such that the first signal path can be interrupted in dependence on the selection signal ENB. The inverter 246 of the second signal path is activated through a selection signal EN, such that the second signal path can be interrupted in dependence on the control signal EN. The outputs of the first signal path and of the second signal path are brought together to form one signal output of the inverting means 240. The signal output of the inverting means 240 is connected to an output register 250, which is likewise of an inverting design.
Through an appropriate activation of the inverting means 240 by means of the selection signals ENB and EN, a situation is achieved in which either the first signal path from the signal measuring amplifier 230 to the output register 250 is switched-through, or the second signal path from the signal measuring amplifier 230 to the output register 250 is switched-through. Since the first signal path provides for a double inversion of its input signal, whereas the second signal path provides for a single inversion of its input signal, the value read out via one of the bitlines BL0-BL7 can thus be selectively inverted through the inversion means 240.
The selection signals ENB and EN for the inverting means 240 are generated by a control logic 220 which, in dependence on input signals S0-S7, generates the selection signals ENB and EN in such a way that they are complementary to one another. The input signals S0-S7 are respectively assigned to one of the bitlines BL0-BL7. For a bitline BL0-BL7 having an inverted assignment, the input signal S0-S7 is provided by the corresponding sub-signal Y0-Y7 of the column multiplexer 210. For bitlines BL0-BL7 having a non-inverted assignment, the input signal S0-S7 is derived from a fixed potential, which differs from the signal level used in the case of the sub-signals Y0-Y7 used in the case of the sub-signals Y0-Y7 for activating the switching means 214. The input signals S0-S7 thus correspond to the bitline inversion coding data.
The input signals S0-S7 are supplied to a logic gate 222 which, depending on whether one of the input signals S0-S7 has a value differing from the fixed potential, first generates the control signal ENB as an output signal. The control signal ENB is then further supplied to an inverter 224, the output signal of which then constitutes the control signal EN. In this case, the logic gate 222 is a NOR gate.
The known solution, described above, for the decoding of data stored using a bitline inversion coding thus requires a complex logic circuit, which means a large amount of control resource and increases the required area for realization on a semiconductor chip. Furthermore, power consumption of the storage is also increased, and the speed of read-out operations and the time control of read-out operations of the storage are impaired. This is due to, inter alia, the substantial additional load to which the sub-signals of the control signal of the column multiplexer 210 are subjected. Consequently, the advantages of bitline inversion coding cannot be exploited to the full extent.